1. Field of the Invention
The present invention generally relates to a semiconductor process, and more particularly, to a method for fabricating a semiconductor device having ultra-shallow source/drain extensions and improved hot carrier immunity ability.
2. Description of the Prior Art
In order to fulfill the requirements of continued device scaling down, it is always very important to utilize low thermal budget processes when fabricating deep submicron devices. Low thermal budget processes result in thinner doping regions in metal-oxide-semiconductor (MOS) transistor devices, which is proved of great benefit to prevent the MOS transistor devices from short channel effect. In the MOS transistor devices, a P-type metal-oxide-semiconductor (PMOS) transistor device tends to have a more severe short channel problem than an N-type metal-oxide-semiconductor (NMOS) transistor device because P-type dopants exercise more quickly than N-type dopants. By properly controlling the depth and profile of the source/drain (S/D) extension, the short channel phenomenon is effectively inhibited.
Please refer to FIG. 1 to FIG. 4. FIG. 1 to FIG. 4 are schematic diagrams of forming a semiconductor device 10 having ultra-shallow S/D extensions according to the prior art. As shown in FIG. 1, a semiconductor substrate 11 is provided first. The substrate 11 is a P-type substrate, and the substrate has two N wells 13, 15. A plurality of gate structures 12, 14, 16, 18 are included on a surface of the semiconductor substrate 11. Each of the gate structures 12, 14, 16, 18 comprises a polysilicon gate 22 and a gate dielectric layer 24 interposed between the polysilicon gate 22 and the substrate 11. In addition, each of the gate structures 12, 14, 16, 18 having sidewalls 26.
First, a dielectric layer (not shown) is formed on the substrate 11 to cover the gate structures 12, 14, 16, 18. Then, a dry etching process is performed to vertically remove the dielectric layer (not shown) down to the surface of the substrate 11. An offset spacer 28 is thus formed on each of the sidewalls 26 of the gate structures 12, 14, 16, 18. Actually, the gate structures 12, 14, 16, 18 are surrounded by the offset spacers 28 if this figure is shown in a three-dimensional form.
Since the gate structure 12 is a gate of an input/output (I/O) PMOS (not shown) and the gate structure 14 is a gate of an I/O NMOS (not shown), two I/O extension implantations are necessarily performed to them. As shown in FIG. 2, an N-type I/O extension implantation process is performed, by utilizing a photo mask (not shown) and the gate structure 14 as a mask, to form an N-type S/D extension 32 in the substrate 11 next to each of the offset spacers 28 on each of the sidewalls 26 of the gate structure 14. After that, a P-type I/O extension implantation process is performed, by utilizing a photo mask (not shown) and the gate structure 12 as a mask, to form a P-type S/D extension 34 in N well 13 next to each of the offset spacers 28 on each of the sidewalls 26 of the gate structure 12. Because both the N-type S/D extension 32 and the P-type S/D extension 34 are very shallow, they are very helpful in preventing the I/O PMOS (not shown) and the I/O NMOS (not shown) from short channel phenomenon.
Since the gate structure 16 is a gate of a core PMOS (not shown) and the gate structure 18 is a gate of a core NMOS (not shown), two other implantations are necessarily performed to them to form lightly doped drains. As shown in FIG. 3, a first N-type ion implantation process is thereafter performed, by utilizing a photo mask (not shown) and the gate structure 18 as a mask, to form an N-type lightly doped region 36 in the substrate 11 next to the offset spacer 28 at either side of the gate structure 18. Then, a first P-type ion implantation process is performed, by utilizing a photo mask (not shown) and the gate structure 16 as a mask, to form a P-type lightly doped region 38 in the N well 15 next to the offset spacer 28 at either side of the gate structure 16.
In addition, at least one angled ion implantation process is performed to form an N-type pocket doping region 42 in the N well 13 at either side of the gate structure 12, a P-type pocket doping region 44 in the substrate 11 at either side of the gate structure 14, an N-type pocket doping region 46 in the N well 15 at either side of the gate structure 16, and a P-type pocket doping region 48 in the substrate 11 at either side of the gate structure 18. The P-type pocket doping regions 44, 48 and the N-type pocket doping regions 42, 46 are used for preventing MOS devices from punch-through phenomenon. Later, a silicon nitride layer 52 is formed on the surface of the substrate 11 to cover the gate structures 12, 14, 16, 18 and the offset spacers 28 on each of the sidewalls 26 of the gate structures 12, 14, 16, 18.
As shown in FIG. 4, an etching process is performed to vertically remove the silicon nitride layer 52 down to the surface of the substrate 11 so as to form a spacer 54 at sides of the gate structures 12, 14, 16, 18. Actually, the gate structures 12, 14, 16, 18 are surrounded by the spacers 54 if this figure is shown in a three-dimensional form. After that, at least one N-type ion implantation process and at least one P-type ion implantation process are performed. As a result, a P-type source/drain region 56 in the N well 13 next to the spacer 54 at either side of the gate structure 12, an N-type source/drain region 58 is the substrate 11 at either side of the gate structure 14, a P-type source/drain region 62 in the N well 15 at either side of the gate structure 16, and an N-type source/drain region 64 in the substrate 11 at either side of the gate structure 18 are formed. Finally, a rapid thermal process (RTP) is performed to drive-in all of the dopants so that the fabrication of the I/O PMOS 66, the I/O NMOS 68, the core PMOS 72, and the core NMOS 74 is completed.
Although the prior method can fabricate a semiconductor device having ultra-shallow S/D extensions to improve it's short channel performance. However, a new problem emerges. When the P-type S/D extension 34 is very shallow, the N-type S/D extension 32 is even shallower. With such a shallow N-type S/D extension 32, the junction depletion region also tends to be narrow. Therefore, the electric field across the junction depletion region is very high since the electric field across the junction depletion region inversely varies with the depletion region width, i.e. the shallower the N-type S/D extension is, the higher the electric field across the junction depletion region is. Therefore, the hot carrier immunity ability of the I/O NMOS, which needs a high voltage to conduct and is conducted owing to the movements of electrons, is obviously degraded to cause problems.
Therefore, it is very important to develop a new process for fabricating the semiconductor device having ultra-shallow S/D extensions. The method should not only fabricate the semiconductor device having well-controlled ultra-shallow S/D extension profiles, but also should fabricate the semiconductor device having improved hot carrier immunity ability.